cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 42

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Introduction
Table 1-9. CX28560 POS-PHY Interface (Receive) (2 of 2)
1-24
RMOD[1:0]
RSOP
FRSOP
REOP
FREOP
RPRTY
FRPRTY
RCLAV
FRCLAV
Note(s):
1. The Receive Start of Transfer (RSX) pin is supported by the standard POS-PHY, but are not required because the CX28560
2. The CX28560 architecture guarantees that the RERR pin, if implemented, would never be asserted. Therefore, to comply fully
Pin Name
supports only packet-level transfers on a single PHY basis.
with POS-PHY, the system should tie RERR to zero.
I/O
O
O
O
O
O
RFCLK
FRFCLK
RFCLK
FRFCLK
RFCLK
FRFCLK
RFCLK
FRFCLK
Ref Clk
RFCLK
Mindspeed Technologies™
Receive Word Modulo (RMOD) signal. RMOD[1:0] indicates the number of valid
bytes of data in RDAT[31:0]. The RMOD bus should always be all zero, except
during the last double-word transfer of a packet on RDAT[31:0]. When REOP is
asserted, the number of valid packet data bytes on RDAT[31:0] is specified by
RMOD[1:0]:
RMOD[1:0] = 00 RDAT[31:0] valid
RMOD[1:0] = 01 RDAT[31:8] valid
RMOD[1:0] = 10 RDAT[31:16] valid
RMOD[1:0] = 11 RDAT[31:24] valid
When the FlowConductor 8-bit interface, the RMOD bus is not considered.
RMOD[1:0] is considered valid only when RVAL is asserted
Receive Start of Packet (RSOP/FRSOP) signal. RSOP/FRSOP delineates the packet
boundaries on the RDAT/FRDAT bus. When RSOP/FRSOP is high, the start of the
packet is present on the RDAT/FRDAT bus. RSOP/FRSOP will be present at the end
of every packet and is considered valid when RVAL/FRVAL is asserted.
Receive End Of Packet (REOP/FREOP) signal. REOP/FREOP delineates the packet
boundaries on the RDAT/FRDAT bus. When REOP/FREOP is high, the end of the
packet is present on the RDAT/FRDAT bus. On the data 32-bit interface, RMOD[1:0]
indicates the number of valid bytes the last double word is composed of when REOP
is asserted. On the FlowConductor 8-bit interface, the last byte of the packet is on
FRDAT[7:0] when FREOP is asserted. REOP/FREOP is required to be present at the
end of every packet and is considered valid only when RVAL/FRVAL is asserted.
Receive Parity (RPRTY/FRPRTY) signal. The receive parity (RPRTY/FRPRTY) signal
indicates the parity calculated over the RDAT/FRDAT bus. On the FlowConductor 8-
bit interface, the CX28560 only supports FRPRTY calculated over FRDAT[7:0]. The
CX28560 supports parity calculation.
Receive Cell Available (RCLAV/FRCLAV). RCLAV/FRCLAV indicates when the
System device has data to transfer. This signal is only relevant in Registered mode
(see
Chapter
Advance Information
2.0).
Description
CX28560 Data Sheet
28560-DSH-001-B