cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 134

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
5.8.6
Table 5-45. TBUFFC Data FIFO Size Register
5.8.7
Table 5-46. TBUFFC Flexiframe Slot Time Register
5-44
31:13
31:8
12:0
Bit
7:0
Bit
RSVD
TNumCycleSlot
RSVD
TDfifoSize
Field Name
Field Name
TBUFFC DATA FIFO Size Register
TBUFFC Flexiframe Slot Time Register
Value
This register defines the size of each channel’s data FIFO in Dwords (4 bytes). This
size is fixed once for the transmit direction since all the channels are allocated the
same amount of buffer memory regardless of their bit rate. The size of the buffer
should be allocated as a multiple of 4, minimum 80 bytes per channel and maximum
32 KB (see
Number of Cycles per Slot
time. Per slot time, one fragment is received and one transmission report. Range from
6–255 clock cycles.
Value
—
0
—
0
Reserved.
Size of Data FIFO per channel in Dwords. The value in this register applies to all channels.
Reserved.
Minimum number of cycles allocated per Flexiframe slot.
This count is zero based, and has a minimum of 0 and a maximum of 255. If this is larger
than three plus the number of Dwords ready to be sent to the system, a gap will be
created between fragments. The aim of this is to allow the system to fix the amount of
time it needs to perform regular (and irregular activities).
When configured to 0, the TBUFFC will work in “fastest possible” mode, i.e., each slot will
take a minimum of 6 cycles.
Appendix
Mindspeed Technologies™
Advance Information
E).
—
a number in clock cycles that indicates the minimum slot
Description
Description
CX28560 Data Sheet
28560-DSH-001-B