cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 269

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

H.1
H.2
H.2.1
28560-DSH-001-B
Overview
Analysis
Internal Considerations
Appendix H: PCI Utilization
This appendix will provide the system with an approximation of the utilization of one
CX28560 on the 32 bit, 33 MHz PCI bus. The calculations can be extrapolated, or
tailored to the actual needs of the system.
It is assumed that the interrupts being written by the CX28560 to the shared memory
has a negligible affect on the PCI utilization. In addition, the configuration of internal
registers is also considered a negligible factor on the overall PCI Utilization. The
major contributors to the CX28560 PCI activity are the writing of Flexiframes to the
CX28560 (at 21 K entries each) and the reading of all the channels’ counters once per
second.
The time to perform a write or read of 32 bits is the total of:
Hence the total time taken to perform one host service routine is 1600 ns (per 32-bit
register).
• Internal wastage:
• PCI bus time:
– This includes time for processing commands, internal bus time, and
– 70 clocks @ 100 MHz = 700 ns
– The calculation below allows each entry in the Flexiframe to be written, and
– 30 clocks @ 33 MHz = 900 ns
reaction time by the blocks. This is not a maximum figure, because no
absolute maximum exists, only a statistical maximum.
each counter to be read in separate descriptors. In addition, it allows for >20
cycle latency.
Mindspeed Technologies™
Advance Information
H
-
1