cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 91

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

5.1
5.1.1
28560-DSH-001-B
Memory Architecture
Register Map and Shared Memory Access
5.0 The CX28560 Memory
The CX28560 interfaces with a system host by the transfer of data as fragments of
packets over a dedicated data bus. The CX28560 also contains a set of internal
registers that the host can configure over a PCI bus, which control the CX28560. In
addition, a unidirectional flow control bus is used to monitor the amount of data in the
CX28560’s internal transmit buffers. This section describes the various data headers,
flow control packets and the layout of individual registers that are required for the
operation of the CX28560.
The CX28560 transfers data as fragments of packets prefixed with a fragment header.
The fragments are transferred to the host over a dedicated data bus.
Configuration commands and monitoring information are stored in a shared memory
from which both the host and the CX28560 write and read. This assumes a system
topology in which a host and the CX28560 both have access to shared memory for
data control. The host allocates and de-allocates the required memory space.
During the CX28560's PCI initialization, the system controller allocates a dedicated 1
MB memory range to the CX28560. The memory range allocated to the CX28560
must not map to any other physical or shared memory. Instead, the system
configuration manager allocates a logical memory address range and notifies the
system or bus controllers that any access to these ranges must result in a PCI access
cycle. The CX28560 is assigned these address ranges through the PCI configuration
cycle. Once configured, the CX28560 becomes a functional PCI device on the bus.
As the host accesses the CX28560's allocated address ranges, the host initiates the
access cycles on the PCI bus. It is up to individual the CX28560 devices on the bus to
claim the access cycle. As the CX28560's address ranges are accessed, it behaves as a
PCI slave device while data is being read or written by the host. The CX28560
responds to all access cycles where the upper 12 bits of a PCI address match the upper
12 bits of the CX28560’s Base Address register (see
Address 10h).
For the CX28560, a 1 MB-memory space is assigned to the CX28560 Base Address
register, which is written into PCI configuration space Address 10h, register 4 in PCI
Configuration registers. Once a base address is assigned, a register map is used to
access individual device resident registers. The CX28560 cannot respond to an access
cycle that the CX28560 itself initiates as the bus master. The register map provides the
byte offset from the Base Address register where registers reside. The register map
Organization
Mindspeed Technologies™
Advance Information
Chapter
2.0, PCI Register 4,
5
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