cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 244

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

TSBUS
D.2.3
Figure D-5. Payload Time Slot Bus Receive Data (TSB_RDAT)
D-10
TSB_RDAT
TSB_CLK
Receive Timing
T
The TSBUS device operates as the master of the receive TSBUS and the
CX28560 device responds as slave. The TSBUS generates clock, data, Frame
sync signal, and the Stuff signal. The TSBUS generates an all ones stuff pattern in
place of the payload data during the same time slot that the Stuff signal is active.
The TSBUS generates control and data outputs synchronously with the rising
edge of TSB_CLK. The nominal clock frequency is 51.84 Mbps.
shows the timing requirements for the receive interface. See
Stuff signal.
pwh
Receive Bit n
T
per
Mindspeed Technologies™
T
pwl
Advance Information
Receive Bit n+1
Receive Bit n+2
Figure D-6
Figure D-5
CX28560 Data Sheet
28560-DSH-001-B
for the