cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 131

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
5.8.3
Table 5-42. TBUFFC Channel Configuration Register
28560-DSH-001-B
31:30
29:13
12:0
Len
33
32
TCMDCIEN
TBOVFLWIEN
TPROTOCOL
TSTARTADD
TTHRESHOLD
Field Name
TBUFFC Channel Configuration Register
This register controls the operation mode for a channel. It contains parameters
necessary for the division of the internal memory to channel FIFOs. There is one
Channel Configuration Register for each logical channel (i.e., 2047).
The CX28560’s internal Tx memory is a 384 KB dual RAM, which may be split to
2047 parts, one part for each channel. The allocation granularity is one Dword
(4 bytes).
In the CX28560, regardless of its bit rate, each channel receives an identical
allocation of memory. The difference in bit rates is accounted for by extra servicing of
faster channels according to the Flexiframe algorithm. Hence the length of a channel’s
buffer is set once (see
specify the start address of the internal data buffer.
Since this register is wider than 32 bits, it spreads over 2 consecutive addresses. When
writing to this register, the first 32 least significant bits are written to the first address
and the upper bits are written to the lowest possible bits in the second address.
NOTE:
Value
—
—
0
1
0
1
0
1
2
3
The host must set the buffers so there is no overlap between buffers belonging
to different channels. Each receive channel must be allocated buffer space
before the channel can be activated.
End of Channel Command Execution Interrupt Disabled.
End of Channel Command Execution Interrupt Enabled.
On completion of command (activation or deactivation) an interrupt will be generated.
TBUFFC Channel Buffer Overflow Interrupt Disabled.
TBUFFC Channel Buffer Overflow Interrupt Enabled.
FCS Protocol. This should be the same as the corresponding TSLP configuration.
TRANSPARENT
HDLC with no FCS
HDLC with 16 bit FCS
HDLC with 32 bit FCS
Channel DATA FIFO Start Pointer—0 based.
The addresses are allocated in Dword (4-byte) granularity.
Channel Buffer Threshold Level.
The CX28560 will not start to transmit a new message until THRESHOLD number of
Dwords (4 bytes) are stored in the channels internal buffer. If the message to be
transmitted is less than the threshold, the CX28560 will start to transmit the message
when the end of message is detected (threshold is a zero based count).
Mindspeed Technologies™
Advance Information
Table
5-45). However, for each active channel it is required to
Description
The CX28560 Memory Organization
5
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41