cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 170

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Basic Operations
7.2.9.7
7.2.9.8
7-12
Long Message (LNG)
The received HDLC message length is determined to be greater than the maximum
allowable message size per the MAXSEL bit field in
Message Length register.
Reason:
Effects:
Channel-Level Recovery Actions:
Short Message (SHT)
The total received HDLC message size (between open/close flags) is determined to be
less than the number of FCS bits specified for that channel plus one octet. For
example, a channel configured for 16-bit FCS must receive a minimum of three
octets—one octet of payload and two octets of FCS—to avoid a short message error.
In this example, receiving only two octets is considered a short message.
NOTE:
NOTE:
Reasons:
Effects:
• Incorrect message transmission from distant end.
• EOM Interrupt with RxLNG error status (if ERRIEN = 1 in
• When the message reaches the top of the internal FIFO, the HDLC message—
• The RSLP scans for the opening flag of the next HDLC message.
• RBUFFC is not affected and continues to transfer message data to the host.
• None required.
• Bit errors during transmission.
• Incorrect message transmission from distant end.
• RxSHT Interrupt (if IDLEIEN = 1 in
• RSLP resumes scanning for opening flag of the next HDLC message.
RBUFFC Configuration register and
register).
up to the maximum legal length—is transferred to the host, and the last
fragment header of the message is written with ERROR = LNG.
Any message that ends with an error (any error except an overflow) and for
which the entire message (regardless of its length) still resides in the internal
SLP buffer (meaning no data has yet been transferred to the internal channel
FIFO), the CX28560 generates a SHT interrupt and does not transfer any of
that message to a shared memory buffer. In this case, no other indication is
given for the errored message.
Because the RxSHT interrupt in this case is reported immediately, its interrupt
descriptor can arrive in the shared memory interrupt queue before an earlier
message that remains queued in the internal BUFFC channel FIFO. Hence,
interrupts from these two messages may appear out of sequence with respect to
their actual order of arrival.
Configuration register).
Mindspeed Technologies™
Advance Information
Chapter
Chapter
5.0, TBUFFC Configuration
5.0, RSLP Channel
Chapter
5.0, RSLP Maximum
Chapter
CX28560 Data Sheet
28560-DSH-001-B
5.0,