cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 27

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
28560-DSH-001-B
Unchannelized mode
Variable path primitives are supported.
Per-channel protocol selection is supported.
Dynamically configurable logical channels are supported.
Programmable time slot allocation is supported.
Per-channel BUFFC buffer management is supported.
Clear to Send (CTS) per-channel control of data transmission in conventional
mode ports.
Direct POS-PHY bus interface is supported.
PCI Bus Interface (rev. 2.2) for configuration purposes only.
Applications that require unchannelized ports:
Path Payload
Higher speed ports
Path overhead (Performance Monitoring and Provisioning)
Non-FCS mode
16-bit FCS mode
32-bit FCS mode
Transparent mode
Standard DS0
Hyper-channel
Sub-channel
Pointer mechanism
Internal FIFO of size 352 KB in the transmit direction and 320 KB in the
receive direction.
One size of channel FIFO required regardless of channel bit rate (allows for
dynamic reconfiguration of specific channels without full chip reset)
Configurable BUFFC threshold set on a per-channel basis in the transmit
direction
Programmable FIFO size per-chip basis
32-bit multiplexed Address/Data bus minimizes pin count
33 MHz operation
– Digital Comm/Termination Equipment (DCE/DTE) Interfaces
– High Speed Serial Interface (HSSI)
– Inter-Process Communication (IPC)
– V-Series DTE/DCE Interfaces (V .35)
– SDSL Modems and Access Concentrators
– T3/E3 Frame Relay
– DS-0 (64 Kbps)
– Nx64, where N is defined as any number between 1– 810, allows all types
– Unchannelized DS3 (44.736 Mbps)
– Unchannelized E3 (34.368 Mbps)
– HSSI (52 Mbps)
– T1/E1
– Facilities Data Link (FDL)
– Common Channel Signaling (CCS)
– T3/E3 Terminal Data Link (TDL)
– V .51 and V .52 signaling channels
of hyper-channeling, channelized, unchannelized, or path payload
Mindspeed Technologies™
Advance Information
Introduction
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