cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 93

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
Table 5-2. Indirect Register Map Address Accessible via Service Request Mechanism (1 of 2)
28560-DSH-001-B
RBUFFC Flexiframe Memory
RBUFFC Counter Memory
RBUFFC Channel Configuration Register
RBUFFC DATA FIFO Size Register
RBUFFC Flexiframe Control Register
RBUFFC Fragment Size Register
RBUFFC Flexiframe Slot Time Register
RSLP Channel Status Register
RSLP Channel Configuration Register
RSLP Maximum Message Length Register 1
RSLP Maximum Message Length Register 2
RSLP Maximum Message Length Register 3
RSIU TS/Group Map
RSIU Group Map
RSIU Group Map Pointer Allocation Register
RSIU Group State Register
Register (BAR)
Base Address
Configuration
Register 4
CX28560
PCI
Register
Table 5-1. PCI Register Map (Direct Access)
Receive Port Alive Register
Transmit Port Alive Register
Interrupt Status Register
Interrupt Queue Pointer
Interrupt Queue Length
Service Request Length Register
Service Request Pointer Register
Soft Chip Reset Register
NOTE(S):
1. There are two address spaces: The first address space includes registers that are directly
2. Although the post reset value of the Service Request Length is 0, until the CX28560 has finished
accessed by host through the PCI. The second address space (shown in
the CX28560’s register map accessible to the Service Request Mechanism. Therefore, all the
registers shown in this table can be directly read or write by the host.
all initializations, the value shown in the SRQ_LEN field of this register will be all 1s.
Mindspeed Technologies™
Register
Advance Information
Access
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
Access
Type
R/W
R/W
R/W
R/W
R/W
WO
RO
RO
000000–0053FF
008000–00BFFF
00C000–00C7FF
00FFFB
00FFFC
00FFFD
00FFFE
050800–050FFF
051000–0517FF
053FFD
053FFE
053FFF
094000–095FFF
096000–097FFF
098000–0981FF
098200–0983FF
Descriptor
(22 bits)
Address
0000Ch
00000h
00004h
00008h
00010h
00014h
00018h
00020h
Offset
Byte
21K Per Chip
8 Per Channel
1 Per Channel
1 Per Chip
1 Per Chip
1 Per Chip
1 Per Chip
1 Per Channel
1 Per Channel
1 Per Chip
1 Per Chip
1 Per Chip
8K Per Chip
8K Per Chip
1 Per Group (512)
1 Per Group (512)
The CX28560 Memory Organization
(bit) Per Port
(bit) Per Port
Number of
Number of
Instances
Instances
Per Chip
Per Chip
Per Chip
Per Chip
Per Chip
Per Chip
Table
5-2) represents
Value
Reset
Reset
Value
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
5
-
3