cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 148

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Functional Description
6.1.1.1
6.1.1.2
6-2
Hard PCI Reset
The PCI reset is the most thorough level of reset in the CX28560. All subsystems
enter into their initial states. PCI reset is accomplished by asserting the PCI signal,
PRST*.
The PRST* signal is an asynchronous signal on the PCI bus. The reset signal can be
activated in several ways. The system must always assert the reset signal on power-
up. Also, a host bus to PCI bus bridging device should provide a way for software to
assert the reset signal. Additionally, software-controlled circuitry can be included in
the system design to specifically assert the reset signal on demand.
Asserting PRST* towards the CX28560 guarantees that data transfer operations and
PCI device operations does not commence until after the CX28560 has been properly
initialized for operation. Upon entering PCI reset state, the CX28560 outputs a three-
stated signal on all output pins and halts activity on all subsystems including the host
interface, serial interface, and expansion bus. The effects of a PCI reset signal within
the CX28560 takes ten PCI clock cycles to complete. After this time, the host may
communicate with the CX28560 using the PCI configuration cycles.
After the PCI configuration, the device is not ready to start communication with the
host via the service request mechanism until the SRQ_LEN bit field in Service
Request register is set to zero.
Soft Chip Reset
A soft chip reset is a device-wide reset without the host interface’s PCI state being
reset. Serial interface operations and EBUS operations are halted. The soft chip reset
state is entered in one of two ways:
A soft chip reset causes the following:
The host acts as if this was a PCI reset, except that the PCI configuration does not
need to be repeated (is kept unchanged).
The host can assume that the reset was completed by the CX28560 and can start
configuration of registers when the field SRQ_LEN is zero.
1.
2.
• Transmit data signals, TDAT, to be three-stated
• EBUS address-data lines to be three-stated and read enable and write enable
• All active channels to enter the channel deactivated state
• Buffer controllers to be reset, halting all POS-PHY transactions
• All the bits in the Interrupt Status register to clear
• SRQ_LEN and bits in Global Configuration Descriptor to clear
As a result of the PCI reset
As a result of a soft chip reset host service request
outputs to be deasserted, halting all memory operations on EBUS
Mindspeed Technologies™
Advance Information
CX28560 Data Sheet
28560-DSH-001-B