cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 46

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Introduction
Table 1-12. Boundary Scan and Test Access
Table 1-13. Performance Monitoring
1-28
TCK
TRST
TMS
TDO
TDI
TM[3:0]
ONESEC
Pin Name
Pin Name
I/O
I/O
O
I
I
I
I
I
I
Ref Clk
Ref Clk
TCK
TCK
TCK
TCK
—
—
—
Mindspeed Technologies™
JTAG Clock (TCK). Used to clock in the TDI and TMS signals and as clock out
TDO signal.
JTAG Enable (TRST). An active-low input used to put the chip into a special test
mode. This pin should be pulled up in normal operation.
JTAG Mode Select (TMS). The test signal input decoded by the TAP controller to
control test operations.
JTAG Data Output (TDO) The test signal used to transmit serial test instructions
and test data.
TDI JTAG Data Input (TDI) The test signal used to receive serial test instructions
and test data.
Test Mode (TM). Encodes tests modes (must be pulled low in normal operation).
An asynchronous pulse provided as an input to CX28560 that causes the latching
of the performance monitoring counters. Not necessarily on one-second
boundaries.
Advance Information
Description
Description
CX28560 Data Sheet
28560-DSH-001-B