cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 152

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Functional Description
6-6
Configuration Write
Request Procedure
NOTE:
A detailed typical configuration write request procedure is
NOTE:
The registers initialized through the Service Request Mechanism are as follows:
7.
8.
1.
2.
3.
4.
5.
If the port is not alive in 16 system clocks then there are no serial clocks
applied specific port.
Initialize the Service Request Pointer (SRP) and Service Request Length
(SRL) registers by performing a direct write to the CX28560 Service Request
Pointer and Service Request Length register and update the value with the
address all the SRP table and its length in shared memory.
Perform a CONFIG_WR Service Request and wait for the SACK or EOC (End
of Command) indication which copies the content of the register in shared
memory to the relevant CX28560 internal register. The host can perform one
CONFIG_WR Service request given that all the register have been initialized
in the shared memory prior to the CONFIG_WR Service Request, or can
perform CONFIG_WR Service Request for each register individually.
Allocate the Service Request table in the shared memory.
This allocation can be done in the very beginning (see step 3 or in the
configuration write request procedure)
Initialize the content of the Service Request Table.
Initialize the Service Request Pointer (SRP) with the address of Service
Request table by performing a direct write to the Service Request Pointer
register.
Start the execution by writing the table length into to the Service Request
Length register by performing a direct write.
If other Service Request table is required, the host must poll the Service
Request Length register by performing a direct read and check the SRQ_LEN
field. If this fields is not zero, the CX28560 did not complete the execution of
the last Service Request Table. The number written in the SRQ_LEN indicates
how many Configuration Write commands (i.e., table entries) are pending for
execution. While processing these commands, the CX28560 generates a SACK
interrupt for each command in which the SACKIEN bit was set. When
SRQ_LEN becomes 0, the host may start from Step One in
Write Request
memory which was allocated for the prior Service Request table or uses the
same memory as a pool memory.
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
k.
Global Configuration [1] (one per chip)
EBUS configuration [1] (one per chip)
RSLP Channel Configuration [2047] (one for each channel which is going
to be activated)
RSLP Max. Message Length [3] (three registers)
RBUFFC Configuration [2047] (one for each channel which is going to be
activated)
RBUFFC Flexiframe Memory [1] (one per chip)
RBUFFC Data FIFO Size [1] (one per chip)
RBUFFC Fragment Size [1] (one per chip)
RBUFFC Slot Time [1] (one per chip)
RBUFFC Flexiframe Control [1] (one per chip)
RSIU Time Slot/Group Map [8192] (for each time slot that is going to be
used)
Mindspeed Technologies™
Advance Information
Procedure, whereas prior to a new execution either frees the
Configuration
CX28560 Data Sheet
28560-DSH-001-B