cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 3

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Advance Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
CX28560
HDLC Controller
The CX28560 is an advanced Multichannel Synchronous Communications Controller
(MUSYCC™ ) that formats and deformats up to 2047 HDLC channels in a CMOS
integrated circuit. MUSYCC operates at Layer 2 of the Open Systems Interconnection
(OSI) protocol reference model and provides a comprehensive, high-density solution
for processing HDLC channels for inter-networking applications.
All packet data passed between the system and the CX28560 is passed across the
POS-PHY interface (POS-PHY). The POS-PHY operates in packet mode as a 32-bit
wide point-to-point interface at 100 MHz. Data is transferred in fragments of user-
configurable length (minimum 32 bytes per fragment).
The CX28560 supports a PCI interface for initial configuration as well as to perform
dynamic activation and deactivation of channels. In addition, the CX28560’s
configuration and performance monitoring counters can be read over the PCI
interface.
The scheduling system for the receive and transmit data flow is based on the unique
Flexiframe™ algorithm. Flexiframe enables efficient memory utilization and provides
support for various channels operating at extremely different rates. Flexiframe allows
dynamic resizing of every channel’s rate without affecting the other channels. The
order in which message fragments are transferred across the POS-PHY is fixed by the
Flexiframe structure, each fragment having been tagged with a 4-byte fragment
header. The fragment header contains the channel number and relevant status
information.
A dedicated 8-bit bus provides the system the necessary feedback to determine the
amount of data contained in each channel’s transmit buffers. This is achieved by the
CX28560 sending requests to the system for more transmit data. In the receive
direction, the CX28560 operates autonomously without any need for system
intervention or guidance.
Functional Block Diagram
28560-DSH-001-B
100 MHz POS-PHY
FlowConductor Bus
Unit-directional 8 b
Bi-directional 32 b,
100 MHz Tx
Bus (Data)
Controller
Interrupt
PCI Bus 2.2
PCI I/F
Controllers
Flexiframe
Scheduler
Internal
Service
Buffer
Host
Unit
EBUS Bridge
Processors
Serial Line
Expansion Bus
Mindspeed Technologies™
and
Rx
Tx
Advance Information
Miscellaneous
JTAG etc.
Interface
Serial
Units
and
Rx
Tx
Port 31
Port 0
Port 1
.
.
.
Distinguishing Features
2047-channel HDLC controller
OSI Layer 2 protocol support
32-bit full duplex standard POS-PHY Level
3 bus
Aggregate bandwidth of 700 Mbps full
duplex
32 bits, 33 MHz PCI 2.2 bus interface for
configuration and monitoring
Dedicated feedback bus for Tx buffers fill
level
32 independent serial interfaces support:
Configurable logical channels
Channels’ bit rate can be dynamically
changed.
Per channel protocol mode selection
Per-channel message length check
HDLC maximum packet length 16,384
bytes
3 separate HDLC modes, configurable per
channel:
Transparent (not HDLC) mode
Autonomous Rx operation and arbitration
between the channels
Selectable endian configuration for control
information (PCI)
Per-channel buffer management
Full set of 10 performance monitoring
counters per channel
Transfer of partial HDLC messages over
the POS-PHY interface
Low power, 1.8 volt core, 3.3 volt I/O,
CMOS operation.
Local expansion bus interface (EBUS) for
accessing non-PCI components (framers,
LIUs)
JTAG boundary scan access port
40 mm TBGA package
T1 data stream
N * 64 Kb/s data stream
TSBUS interfaces
Unchannelized data stream
Standard DS0 (56, 64 Kbps)
Hyperchannel (N x 64)
Select no length checking
Select from three 14-bit registers to
compare message length
no FCS
16-bit FCS
32-bit FCS
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