cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 33

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
28560-DSH-001-B
The following is a description of the block diagram.
• Host Interface (POS-PHY): This block provides the communication path of the
• PCI Host Interface: This block interfaces to the PCI bus over which the host
• Expansion Bus (EBUS): The EBUS is an extension of the PCI Host Interface,
• Serial Interface Unit (SIU): This block provides the interface between 32 serial
• Transmit Serial Line Processor (TSLP): This block provides the interface
• Receive Serial Line Processor (RSLP): This block provides the interface
• BUFFC: This block provides the interface between the host and the Transmit
• JTAG: This is a special test port used for serial boundary scan on a PCB, as
• Onesec: the onesec signal provides the boundaries on which the performance
data between the host and the CX28560.
configures and monitors the CX28560 action.
which provides host with access to control other devices on the local PC board.
ports and the Receive and Transmit Serial Line Processors block. A temporal
buffering space is provided by the SIU that is 56 bits per port, divided as 32 bits
(4 bytes) for the transmit direction and 24 bits (3 bytes) for the receive direction.
SIU controls the data access to the Rx and Tx Serial Line Processors. Because
the CX28560 supports two types of serial ports—one is the conventional
interface, the other TSBUS interface—the SIU needs to operate depending on
serial port type (for detailed descriptor information, see
between the Buffer Controller (BUFFC) and the TSIU. Data provided by the
BUFFC is processed by the TSLP according to the channel type and passed to
the TSIU for transmission to the line.
between the SIU and BUFFC. The data provided by RSIU is processed by
RSLP according to the channel type before it is transferred to the BUFFC.
and Receive Serial Line Processors (TSLP and RSLP). The BUFFC contains
the main storage of data—a dual port RAM of 352 KB in the transmit direction
and 320 KB in the receive direction. This space acts as a holding buffer for
incoming (Rx) and outgoing (Tx) data.
well as access to internal scan paths and embedded memory for test.
monitoring counters are latched.
Mindspeed Technologies™
Advance Information
Chapter
4.0).
Introduction
1
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