cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 60

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Host Interfaces
2.3
2.3.1
2.3.1.1
2.3.1.2
2-14
POS-PHY
POS-PHY Interfaces
There are three POS-PHY interfaces—two for the transfer of data, and one that is
used as a feedback bus to the system.
In addition to the individual configurations necessary for configuration, the POS-
PHY Registered Mode bit in the Global Configuration register
configured.
POS-PHY Registered Mode
The POS-PHY standard sets the timing of the RxENB signal. Normal mode (non-
registered mode) works exactly according to the standard. Non-registered mode delays
the timing of the sampling of the RxENB signal by one clock. In order to use the
CX28560 with the TSP (MXT4700), the POS-PHY should be configured in
registered mode. When in registered mode, the Cell Available (CLAV) signal is also
active. See
POS-PHY Data Interface
In all places where the POS-PHY Data Interface is referred to, the “Transmit side” is
the side on which data is transmitted from the host to the CX28560, and the “Receive
side” is the side on which the CX28560 transmits data to the host.
The POS-PHY Data Bus implemented in the CX28560 is compliant to the ATM POS-
PHY level 3 standard (AF-PHY-0143.000) and supports other industry standards for
Level 3 packet functionality at 100 MHz clock, and 32 bit wide data bus for the
transferal of data fragments. The packet functionality is provided by start of packet
and end of packet signals that delimit the fragments.
NOTE:
Flow control on the Transmit side bus is provided by the PTPA (Polled-PHY Transmit
Packet Available) pin. When there is not enough space in the buffer to receive further
data for transmission, the PTPA pin is set to low. The decision as to whether there is
space in the buffers is decided according to two thresholds: an upper threshold, and a
lower threshold. The buffers are initially empty. Crossing thresholds has the following
affects:
The thresholds are set in the Transmit POS-PHY Thresholds register (see
Transmit POS-PHY Thresholds register).
The upper threshold should be set to the buffer size less the maximum fragment
length. The lower threshold should be set in accordance with the latency of the
mechanism deciding whether to send data.
• Crossing the lower threshold from below has no affect (the PTPA pin remains
• Crossing the upper threshold from below de-asserts the PTPA pin (there is no
• Crossing the upper threshold from above has no affect (there is still no space in
• Crossing the lower threshold from above causes the PTPA pin to be asserted
asserted).
space in the buffer).
the buffer).
(there is now space in the buffer).
The start and end of HDLC packets are indicated in the fragment headers.
Table 1-9, CX28560 POS-PHY Interface
Mindspeed Technologies™
Advance Information
(Receive).
(Section
CX28560 Data Sheet
5.4) should be
28560-DSH-001-B
Chapter
5.0,