cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 147

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

6.1
6.1.1
28560-DSH-001-B
Initialization
Reset
6.0 Functional Description
There are two levels of reset:
There are two ways to assert a reset:
After reset, the host must configure the CX28560 for it to operate. This configuration
includes several stages that should be performed in the following order:
NOTE:
1.
2.
1.
2.
1.
2.
3.
4.
5.
Hard PCI Reset
Soft Chip Reset
Assert the PCI reset signal pin, PRST*.
Assert a service request through the host interface to perform the soft chip
reset.
PCI Configuration—must be performed only after Hard PCI Reset
Interrupt Queue Configuration
Global Configuration
POS-PHY Configuration
Channels and Ports Configuration
The Interrupt Queue must be configured before other registers. If the Interrupt
Queue is not configured with the correct value of Shared Memory Interrupt
Queue Pointer and Interrupt Queue Length, it may result in writes to location 0,
because the Service Request Acknowledge (SACK) is written to a zero address
location.
Mindspeed Technologies™
Advance Information
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