cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 219

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

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28560-DSH-001-B
Overview
Appendix B: Flexiframe Algorithm
The aim of the Flexiframe algorithm is to facilitate the static allocation of internal
memory between channels, such that each channel, regardless of its bit rate, will
require an equal amount of memory (see Appendix E: Calculation of Buffer Size). In
order to do this, channels of a higher bit rate are serviced, in proportion to their bit
rate, more often than lower bit rate channels. A full implementation of the Flexiframe
algorithm is included in the CX28560 drivers (code can be provided on request).
NOTE:
The following description applies to both the receive and transmit Flexiframes.
The Flexiframe algorithm provides a schedule according to which the CX28560
services channels. The Flexiframe is a list of the channels written to the CX28560
memory that, together with various user-configurable registers, fixes the buffer
controller work mode. The Flexiframe is a simple list of channel numbers in slots.
Each slot contains one channel number or NOP command (slot channel number = 0),
and represents one service by the buffer controller.
In the receive direction, during each slot/service a maximum of one fragment of
message data and fragment header will be sent over the POS-PHY to the System.
During a service the buffer of the channel whose number was the next in the
Flexiframe is examined. If the buffer contained either the end of a message or enough
data to form a fragment, data ia sent to the system. The length of the fragment sent is
fixed in a Receive Buffer Controller register (See
In the transmit direction, during each slot/service the transmit buffer controller sends
a report to the system over the Flow Conductor POS-PHY interface regarding the next
channel in the Flexiframe to be served (see Appendix C, Flow Conductor).
The parameters that can be fixed in the CX28560 that control the Flexiframe are as
follows:
The maximum number of 256 bytes per fragment. According to this value, the receive
buffer controller decides whether enough data has been collected to send a fragment.
Enough data is defined to be either the number of 4-bytes as shown in the reference
fragment length register (see
existence of an end of message if one appears before this amount of data is reached.
• Fragment length (Receive only)
• Slot time (receive and transmit)
When all channels are of the same bit rate, the Flexiframe algorithm takes its
most simple form—a list of the channels.
Mindspeed Technologies™
Advance Information
Section 5.7.8 RBUFFC Fragment Size
Chapter
5.0).
Register), or the
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