cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 20

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Introduction
1.1
1.1.1
1.1.1.1
Table 1-1. Supported CX28560 Serial Port Modes (1 of 2)
1-2
Conventional Unchannelized
Conventional Channelized
Conventional T1 mode
TSBUS
(No DS0 Extraction)
TSBUS
(With DS0 Extraction)
CX28560 Serial Port Mode
(2)(4)
(2)(3)
External Interfaces
CX28560 Serial Interface
(1)
(1)(2)
(1)
Each serial port can be configured to support different types of interfaces. Each of the
CX28560’s 32 full-duplex serial ports are individually programmable to operate as
conventional or TSBUS serial ports.
The CX28560 supports five different operating modes for each of its serial ports
(some limitations apply, see below): Conventional Unchannelized, Conventional
Channelized, Conventional T1, TSBUS (no DS0 extraction), and TSBUS (with DS0
extraction). A brief description of each of these modes is listed in
fuller description, see
CX28560 Serial Port Modes Description
In all conventional modes the Group Sync signals are ignored.
The serial input/output data stream is a bit stream without any framing or alignment. The bit
stream belongs to a single logical channel. The CX28560 conventional unchannelized mode
can be configured for all 32 serial ports. The first twelve serial ports can operate
unchannelized T3/E3, HSSI, or STS-1/STM-1 bit stream up to 52 Mbps per serial interface
(for reference, see
The serial bit stream is treated as a frame of N time slots (where N is ≤ 8192, given that
other restrictions are met). The maximum bandwidth embedded into the PCM highway for
the first thirteen ports is STS-1 rate (51.84 Mbps). The byte and frame synchronization
performed is based on receive and transmit sync pulse (RSYNC and TSYNC). (For a detailed
description of these signals, see
The serial bit stream is treated as a frame of 24 time slots and the first bit of each T1 frame
is discarded by the CX28560 hence, if the serial port is configured in T1 mode, the port
operates according to the T1 framing definition.
The TSBUS serial interface bit stream is treated as a frame of N time slots or variable
bandwidth time slots called Virtual Serial Ports (VSPs) where N is defined as ≥ 5, and the
aggregate number of time slots across all ports in any direction does not exceed the 8192
available time slots in each direction, (receive or transmit). Byte synchronization and frame
synchronization is performed based on the TSBUS sync pulse TSTB (i.e., bus strobe).
Mixed T1/E1 paths in one T3, mixed VT1.5/VT2 paths mapped to VTGs in one STS1, and
mixed VC11/VC12 paths mapped to TUG2 in STM-1 are allowed using this serial port
configuration. No DS0 extraction is performed, but separate logical channels can be
configured within the frame.
This mode is identical to TSBUS no DS0 extraction, except that further multiplexing can be
performed by synchronizing T1/E1 frames within the STS-1 bit stream with the Group Sync
pulse (RGSYNC and TGSYNC). According to this pulse, DS0 extraction is performed.
Normally this mode will be used to extract DS0 signals from T1/E1 frames within a higher
multiplexed hierarchy (see
within groups is possible. A minimum of 5 slots must be programmed per group.
Mindspeed Technologies™
Advance Information
Chapter
Section
1.1.1.2).
Appendix D
4.0.
Chapter
for full explanation). Hyper channeling of channels
Description
4.0.)
Table
CX28560 Data Sheet
28560-DSH-001-B
1-1, or, for a