L64704 LSI Logic Corporation, L64704 Datasheet - Page 91

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figure 4.9
PLL Clock
Synthesis
Table 4.1
Table 4.1
CLK/SCLK Ratio
Internal
R = 200 ohms
C1 = 10 nF
C2 = 20 pF
The recommended values for PLL_S, PLL_N, PLL_T, and PLL_M to
cover the frequency range from 2 to 62.5 MHz for PCLK are tabulated in
Table 4.2
PLL Clock Generation
SCLK
.
shows the ratio of CLK to SCLK.
1/(PLL_T)
Group 4, APR 18
CLK_RATIO[2:0]
(Phase Detector
Charge Pump
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
1/(PLL_S)
C1
LP2
VCO)
R
PLL
Loop Filter
PLL_M
External
C2
Group 4, APR 14
CLK_DR[1:0]
PLLAGND
PLL Clock Synthesis
0
0
0
0
0
1
1
1
1
1
2
2
2
2
2
1/(PLL_N)
CLK/SCLK
Ratio
16
32
16
32
64
12
24
48
2
4
8
4
8
3
6
PCLK
Output
Pin
4-7