L64704 LSI Logic Corporation, L64704 Datasheet - Page 71

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.14
Group 4,
APR 15
Clock Loop
Control 2
The Clock Loop Control 2 register is used to set clock parameters related
to the Demodulator module Automatic Frequency Control (AFC) and
external phase-locked loop. It also contains the power-down control bit.
Read/Write: R/W
Set to 0
PCLK_BP
Set to 0
PD
Group 4 Registers
APR
15
Set to 0
D7
PCLK_
Set to 0
You should set this bit to 0 for proper operation.
PCLK Bypass
When you set this bit to 0, the PCLK output pin carries
the clock signal generated by the internal PLL module.
When you set this bit to 1, PCLK presents SCLK at the
output and bypasses the internal PLL module. For a block
diagram see Section
Schemes.”
Set to 0
You should set this bit to 0 for proper operation.
Power-Down
When you set Power-Down to 1, all modules except the
asynchronous microprocessor interface are turned off to
reduce power consumption to a minimum. No data pro-
cessing can occur during Power-Down. When you set
Power-Down to 0 all elements operate. You should apply
a reset pulse after you change Power-Down from 1 to 0
(wake-up) before you start processing data.
Definition
Normal Operation
Device in Power-Down Mode
D1 D0
D6
BP
0
0
1
1
0
1
0
1
Set to 0
D5
Decimation
none
1/2
2/3
Illegal
PD
D4
4.1, “Data Control and Clocking
Oversampling
Ratio
D3
2
4
3
D4
0
1
D2
CLK_RP[3:0]
D1
D0
3-39
7
6
5
4