L64704 LSI Logic Corporation, L64704 Datasheet - Page 64

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.7
Group 4,
APR 8
Viterbi
Maximum Bit
Error Count
3.6.8
Group 4,
APR 9
Synchronization
Word
3-32
Read/Write: R/W
VMBEC specifies the maximum number of (Viterbi symbol errors/128 + 32)
that are allowed to occur within the data period set by VMDC1 (Group 4,
APR 4) to achieve Viterbi module synchronization. Whenever the symbol
error count from the internal bit error counter exceeds the value VMBEC,
the synchronization module concludes that the Viterbi decoder module is
out of synchronization and proceeds to adjust the phase of the incoming
symbol stream until synchronization is reached. For example, a value of
VMBEC[7:0] = 0b00000011
see
Read/Write: R/W
This register contains the synchronization word used by the synchroni-
zation module in stages two and three. Within this byte, the MSB is old-
est chronologically, and the LSB the newest.
Read/Write: R/W
L64704 Registers
APR
APR
APR
APR
APR
5
6
7
8
9
Equation 7.1
D7
D7
D7
D7
D7
Viterbi Maximum Data Bit Count 2, Middle Byte, VMDC2[15:8]
Viterbi Maximum Data Bit Count 2, High Byte, VMDC2[23:16]
Viterbi Maximum Data Bit Count 2, Low Byte, VMDC2[7:0]
D6
D6
D6
D6
D6
in Section
Viterbi Maximum Bit Error Count VMBEC[7:0]
D5
D5
D5
D5
D5
Synchronization Word[7:0]
7.1.4, “Viterbi Bit Error Rate Monitor.”
specifies 416 errors. For more information
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0