L64704 LSI Logic Corporation, L64704 Datasheet - Page 87

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figure 4.2
L64704 Clocking:
External PLL
Figure 4.3
Code Rate = 1/2
System
VCO
A
D
C
CLK
RQ
RI
Figure 4.3
shows a case where the input data rate is 1/2 the data processing rate
in the decoding pipeline. The FEC FIFO input and FIFO output data
streams run at the same rate because no extra information (erasures)
need to be added after the FIFO. The CLK and OCLK signals do not
need to be aligned in phase.
FIFO Output
Data Control and Clocking Schemes
Data Output
L64704
FIFO Input
Viterbi
OCLK
CLK
Demodulator
and
DEMQ
DEMI
Figure 4.4
SCLK
SCLK Selected
1
show several clocking examples.
Sy1
2
Sy1
PLL
Dn
Sy2
3
PCLK
PCLK
Dn+1 Dn+2 Dn+3
Sy2
Sy3
PLL
4
Sy4
Sy3
O
F
F
I
FEC
5
OCLK
Sy4
Figure 4.3
6
4-3