L64704 LSI Logic Corporation, L64704 Datasheet - Page 207

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Table B.10
Group 4 Actual
Configuration
The following paragraphs describe how to program each of the L64704’s
registers.
From
the eighth row from the top: PLL_N = 2, PLL_S = 4, PLL_T = 2,
PLL_M = 0.
Group 4, APR 0 – Set bit D7 to 1 and set bit D6 to 0. Based on line 8
from
Set Group 4, APR 0 to 0xC2.
Group 4, APR 1 – Set bits D7 and D6 to 0. Based on line 8 from
Table
Set Group 4, APR 1 to 0x04.
Group 4, APR 2 – Set IMQ to either 0 or 1, the D6 bit to 1, and QB to
0 for QPSK. Based on line 8 from
Set Group 4, APR 2 to 0x42.
Configuring the L64704 FEC Decoder to the DVB Specifications
APR
10
11
12
13
0
1
2
3
4
5
6
7
8
9
Table
Table 4.2
4.2, set PLL_S to 4.
D7
1
0
1
0
0
0
0
0
0
0
0
1
0
0
4.2, set the PLL_N field to 2.
on
D6
0
0
1
0
1
0
0
0
0
1
0
0
0
0
page 4-8
D5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
for rate 1/2 ICLK = PCLK = 21.3 MHz, select
D4
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Table
D3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
4.2, set PLL_T to 2.
D2
0
1
0
0
0
0
0
1
0
1
0
0
1
0
D1
1
0
1
0
0
0
0
1
0
1
0
0
0
0
D0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
HEX
C2
0F
82
04
00
40
00
00
20
47
01
81
05
00
B-19