L64704 LSI Logic Corporation, L64704 Datasheet - Page 27

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

2.4
Phase-Locked
Loop Interface
FSTARTOUT Frame Start Output
The Phase-Locked Loop (PLL) circuitry multiplies the Channel Clock
Recovery circuit SCLK signal by 2, 3, or 4 times the symbol rate, based
on the Viterbi code rate. The output from the PLL (PCLK) is brought back
into the L64704 on the OCLK pin to clock the FEC Decoder logic. Use
of the PLL is discussed in
LP2
OCLK
PCLK
PLLAGND
Phase-Locked Loop Interface
frame (if the error condition is removed). ERROROUT is
exactly aligned with the output data stream.This pin is set
HIGH after the FEC_RST register bit (Group 4, APR 36)
is asserted.
The L64704 asserts FSTARTOUT during the first bit of
every frame with valid data in Serial Channel Output
mode and during the first byte in Parallel Channel Output
mode. FSTARTOUT is valid only when DVALIDOUT is
HIGH. This pin is set LOW after the FEC_RST register
bit (Group 4, APR 36) is asserted.
Input to VCO
This pin is the input to the internal voltage controlled
oscillator. It is normally connected to the output of an
external RC timing circuit.
Decoder Clock
The positive edge of OCLK is a positive, edge-triggered
clock. The L64704 internally processes data (Viterbi
decoder, Synchronization, Descrambler, Deinterleaver,
Reed-Solomon Decoder) based on OCLK. All data out-
puts (DVALIDOUT, ERROROUT, FSTARTOUT, CO[7:0])
are referenced to OCLK. OCLK is independent of CLK.
PLL Clock Output
The L64704’s internal PLL clock synthesis module gener-
ates the clock signal PCLK. The PLL is driven by the
SCLK internal signal (QPSK symbol clock). The PLL
clock synthesis module can be configured to generate a
PCLK rate that is appropriate for all Viterbi code rates
specified under the DVB standard.
PLL Analog Ground
Analog ground pin for the PLL module. This pin is nor-
mally connected to the system ground plane.
Section 4.4, “PLL Clock Generation.”
Output
Output
Input
Input
Input
2-5