L64704 LSI Logic Corporation, L64704 Datasheet - Page 53

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.5.1
Group 3,
APR 0, 1
RS Corrected
Error Count
3.5.2
Group 3,
APR 2, 3
RS Uncorrected
Error Count
When read, this register presents a count of corrected errors since it was
last reset. When written, the register is reset to zero. CEC is 16-bits long,
where the LSB is found on APR 0, bit 0, and the MSB on APR 1, bit 7.
The CEC counter is incremented each time that a byte is corrected,
independent of the number of bit errors that are encountered in the byte.
It is not incremented when a block is flagged as uncorrectable. The CEC
counter will wrap around when it reaches its maximum count.
Read/Write: R/W
When read, this register presents a count of the uncorrected code words
since it was last reset. When written, the register is set to zero. UEC is
16 bits long, where the LSB is found on APR 2, bit 0, and the MSB on
APR 3, bit 7. The UEC count stops when it reaches its maximum count
(65535), and the counter is reset each time that it is read.
Read/Write: R/W
Group 3 Registers
APR
APR
APR
APR
0
1
2
3
D7
D7
D7
D7
Reed-Solomon Uncorrected Error Count High Byte, UEC[15:8]
Reed-Solomon Uncorrected Error Count Low Byte, UEC[7:0]
Reed-Solomon Corrected Error Count High Byte, CEC[15:8]
Reed-Solomon Corrected Error Count Low Byte, CEC[7:0]
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
D4
D4
D3
D3
D3
D3
D2
D2
D2
D2
Reset Value: 0x0000
Reset Value: 0x0000
D1
D1
D1
D1
D0
D0
D0
D0
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