L64704 LSI Logic Corporation, L64704 Datasheet - Page 156

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figure 7.11
Interleaving/
Deinterleaving
Operation
7.2.1
Deinterleaver
Block Diagram
7-12
Encoder
From
M
2M
(B-1)M
M
The L64704 Deinterleaver module performs periodic deinterleaving. The
user must specify two parameters: B, the desired interleaving depth, and
M, defined as:
The L64704 Deinterleaver features:
The Deinterleaver is comprised of two main modules:
The modules are shown in the block diagram in
The FEC Decoder Pipeline
=
Convolutional deinterleaving
Maximum block length of 204 bytes
Deinterleaving depth of 12
System clock rate up to 62.5 MHz
A set of configurable RAM-based delay lines that implement the
proper delay for individual data bytes
A controller that handles and generates the strobes needed by the
following elements in the data path.
N
----
B
.
Channel
M
2M
(B-1)M
Figure
7.12.
Decoder
To