L64704 LSI Logic Corporation, L64704 Datasheet - Page 90

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figure 4.8
PLL Clock
Generation
4-6
I/Q Data
Using the internal PLL clock feature allows the L64704 to consume the
minimum amount of power.
Internal
The L64704 contains a clock synthesizer to derive OCLK from SCLK
operating in the range of 2 MHz to 62.5 MHz (see
thesized clock is available on the PCLK output pin.
The PLL can be configured to handle clock ratios for the Viterbi code
rates of 1/2, 2/3, 3/4, 5/6, and 7/8. The following four registers must be
set to derive the appropriate clock frequencies:
Channel Interfaces and Data Control
SCLK
Input
PLL_T[4:0], Group 4, APR 2
PLL_N[5:0], Group 4, APR 0
PLL_S[5:0], Group 4, APR 1
PLL_M[1:0], Group 4, APR 3
Domain
SCLK
PLL Clock
Synthesis
FIFO
Output Pin
PCLK
Reed-Solomon Decoder
Viterbi Decoder
Deinterleaver
Descrambler
Domain
OCLK
Input Pin
OCLK
L64704
Figure
Decoded
Data Output
4.9). The syn-