L64704 LSI Logic Corporation, L64704 Datasheet - Page 206

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

B.4
Configuring the
L64704 FEC
Decoder to the
DVB
Specifications
Table B.9
Group 4 Register Map
B-18
APR
10
11
12
13
0
1
2
3
4
5
6
7
8
9
Set to 1
Set to 0
BER
IMQ
D7
BF
Viterbi Code Rate[2:0]
BPS[2:0]
Set to 0
Set to 0
Set to 1
Set to 0
This section presents the steps required to configure the L64704 to the
DVB specifications. The following pages continue the initialization exam-
ple for the following case:
Table B.9
sents the proper configuration for the above system parameters.
L64704 Application Notes
D6
Transmission Rate:
QPSK Clock VCO:
Viterbi Rate:
ICLK:
OCLK:
Viterbi Max Data Bit Count 2, VMDC2[15:8], Middle Byte
Viterbi Max Data Bit Count 2, VMDC2[23:16], High Byte
Viterbi Max Data Bit Count 2, VMDC2[7:0], Low Byte
is the address map for the group 4 registers.
Sync Status Select,
Viterbi Max Data Bit Count 1, VMDC1[7:0]
QB
D5
Viterbi Maximum Bit Error Count[7:0]
SSS[1:0]
Synchronization Word[7:0]
Reserved
Set to 0
TEI
D4
PLL_RESET
42.6 Mbps (21.3 Mbaud)
42.6 MHz
1/2
21.3 MHz
21.3 MHz
Set to 0
Sync States Acq.
OF
D3
SSA[1:0]
PLL_N
PLL_S
Set to 0
PLL_T
D2
Output Selector, OS[2:0]
Sync States Track,
D1
Table B.10
PLL_M[1:0]
SST[1:0]
L[1:0]
DO
pre-