L64704 LSI Logic Corporation, L64704 Datasheet - Page 30

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

2-8
D[7:0]
DTACK
HOST_MODE Serial or Parallel Host Interface Select
INT
READ
SDATA
L64704 Signal Definitions
latch the data from the L64704 on the rising edge of CS.
During a write cycle, CS must go LOW prior to data being
valid from the controller to the L64704. After the data has
met the minimum setup time, the microcontroller takes
CS HIGH to strobe the data. There is a minimum write
time to allow for internal synchronization. Setup and hold
times are measured with respect to the falling edge of
CS.
Data Bus
D[7:0] is the bidirectional data bus; it is the input data bus
when data is written to the chip and the data output bus
when the chip is read in Parallel Host Interface mode
(HOST_MODE pin is HIGH). The data lines are 3-stated
when not being read or written. When Serial Host Inter-
face mode is selected (HOST_MODE pin is LOW), D0 is
used as the Serial Clock signal to synchronize the trans-
fer of serial data on the SDATA pin. The remaining seven
bits of the data bus function as the slave address.
Data Acknowledge
Data Acknowledge is an active-LOW output indicating
that the transaction on the D[7:0] bus has been
completed.
When HOST_MODE is LOW, it selects the Serial Host
Interface mode; when HIGH, it selects the Parallel Host
Interface mode.
Interrupt
The L64704 asserts INT LOW when an internal
unmasked interrupt flag is set. INT remains asserted as
long as the interrupt condition persists and the interrupt
flag is not masked.
Read/Write Strobe
The microcontroller drives READ HIGH to indicate that
the current transaction is a read from the L64704, and
LOW to indicate that it is a write to the L64704.
Serial Host Interface Data
This bidirectional pin is the data input or output pin when
Serial Host Interface mode is selected (HOST_MODE is
LOW).
Bidirectional
Bidirectional
Output
Output
Input
Input