L64704 LSI Logic Corporation, L64704 Datasheet - Page 29

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

2.6
Microcontroller
Interface
PWRP
SYNC/SCLK
The Microcontroller Interface connects the L64704 to a microcontroller.
A[2:0]
AS
CS
Microcontroller Interface
HIGH output increases the carrier VCO frequency. A high
impedance level maintains the carrier VCO frequency.
When CAR_OUT_SEL is set to 1, these pins carry the
CAR_PED.4 and CAR_PED.5 signals.
Power Control
The power control signal is the positive
output used for power control. This signal can drive an
external passive RC filter that feeds the gain control
stage.
Synchronization Status Flag
When the SYNC/SCLK bit (Group 4, APR 14) is set to 0,
the SYNC/SCLK pin indicates the synchronization status
for one of three synchronization modules in the L64704
(Viterbi Decoder sync, DI/RS sync, Descrambler sync).
When HIGH the SYNC/SCLK output indicates the syn-
chronization has been achieved for the chosen sync mod-
ule. When LOW, the SYNC/SCLK output indicates an out-
of-synchronization condition.
When the SYNC/SCLK bit is set to 1, the SYNC/SCLK
pin carries the SCLK signal that is used to clock the
external DAC during low baud rate operation. See
tion 5.6.2.3, “Low Baud Rate Operation”
information.
Address
A[2:0] comprise the decoder address bus. The address
bus is used in conjunction with an eight-bit data bus
D[7:0], a read/write strobe (READ), a chip select strobe
(CS), and an address strobe (AS) to select, read and
write internal registers.
Address Strobe
AS is an active-LOW address strobe input. The L64704
latches the address on A[2:0] on the falling edge of AS.
Chip Select
CS is an active-LOW chip select strobe input. During a
read cycle, the microcontroller must pull CS LOW to
access the on-chip data registers. The controller should
for more
modulated
Output
Output
Sec-
Input
Input
Input
2-7