L64704 LSI Logic Corporation, L64704 Datasheet - Page 110

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Equation 5.1
5-6
A counter in the AFC decrements once for each VCO clock edge during
the reference period defined below. The microcontroller sets the
counter’s initial value using the 16-bit CLK_NF register (Group 4, APR
16:17). If the counter has reached either -2, -1, 0, 1, or 2 at the end of
the reference period, the VCO clock is within the pull-in range; therefore
the AFC sets the CLK_LCF bit to 1 to declare a lock. If the counter value
is greater than 3, the VCO clock frequency is too low; therefore the AFC
drives a positive voltage on the loop output in order to generate a positive
frequency sweep. If the counter value is less than -3, the VCO clock fre-
quency is too high; therefore the AFC drives a low voltage on the loop
output in order to generate a negative frequency sweep.
The reference period is determined by the frequency reference from an
external crystal. The reference period is derived by preloading a refer-
ence counter with the value in the CLK_RP register (Group 4, APR 15).
This defines the reference period in multiples of 1024 clock cycles.
CLK_RP is a 4-bit register, whose value ranges from 0 to 15.
The external crystal frequency f
frequency f
uncertainty in AFC is:
To ensure that the clock recovery loop locks when the Clock Synchro-
nizer switches from acquisition to tracking mode, the uncertainty in AFC
must be lower than the pull-in range of the clock recovery loop.
For CLK_RP = 10 and f
be satisfied for reliable operation.
For example, consider the following frequency values:
Demodulator Module Functional Description
f
-----------------------------------------------
2 kHz.
VCO
1024 CLK_RP
Nominal VCO clock frequency, f
External crystal frequency, f
2 f
Equation 5.1
CLK_RP 1024
XO
VCO
. The recommended value of f
relates the parameters described above and must
XO
=
= 10 MHz, the uncertainty is approximately
f
XO
XO
XO
must be less than half the VCO clock
= 10 MHz
CLK_NF
VCO
= 60 MHz
XO
is 10 MHz and the