L64704 LSI Logic Corporation, L64704 Datasheet - Page 65

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.9
Group 4,
APR 10
BER Monitor
and
Mismatching
Bits in Sync 2
Tracking Mode
This register is used to set the maximum number of mismatching bits
allowed to declare a match when comparing the data stream to the
reference synchronization word during the tracking phase in the second
synchronization stage.
Read/Write: R/W
Set to 0
Reserved
L[1:0]
Group 4 Registers
APR
10
Set to 0
D7
Set to 0
This is an internal test bit and should be set to 0 for
normal operation.
Reserved Bits
These bits are reserved for LSI Logic internal use only.
Reserved bits should always be set to 0, and will produce
random results when read.
Mismatching Bits, Tracking Mode, Sync 2
This field is used to set the maximum number of mis-
matching bits allowed to declare a match when compar-
ing eight bits in the data stream to the reference
synchronization word during tracking phase in the second
synchronization stage. L can be configured from 0 to 2.
A higher value of L results in a smaller probability of loss
of lock due to random noise, a lower value in a higher
probability of loss.
Data
D1
0
0
1
1
D6
Bits
D0
0
1
0
1
D5
Mismatching Bits
Illegal Value
Number of
Reserved
D4
0
1
2
D3
D2
D1
L[1:0]
D0
[6:2]
[1:0]
3-33
7