L64704 LSI Logic Corporation, L64704 Datasheet - Page 72

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.15
Group 4,
APR 16, 17
Nominal
Frequency of
Clock Input
3.6.16
Group 4,
APR 18
Clock Ratio
3-40
CLK_RP[3:0] Reference Period for Clock AFC
A counter in the AFC decrements once each VCO clock edge during the
reference period. Set the counter’s initial value using the 16-bit CLK_NF
register where bit 7 of APR 16 is the MSB, and bit 0 of APR 17 is the LSB.
See
Read/Write: R/W
This register is used to set the input decimation factor for the RI and the
RQ inputs.
Read/Write: R/W
Reserved
CLK_RATIO[2:0]
L64704 Registers
APR
APR
APR
16
17
18
Section 5.5.2, “Clock Acquisition and Tracking Modes”
D7
D7
D7
CLK_RP presets the four MSBs of the reference counter.
See
Modes”
Reserved
These bits are reserved for LSI Logic internal use only.
Reserved bits should always be set to 0, and will produce
random results when read.
Input Decimation Factor for RI and RQ Inputs
This field sets the input decimation factor for the RI and
the RQ inputs. For more information see Section
“Input Decimation.”
D2
0
0
0
D6
D6
D6
Section 5.5.2, “Clock Acquisition and Tracking
Reserved
D1
0
0
1
for details.
D5
D5
D5
D0
0
1
0
CLK_NF[15:8]
D4
D4
D4
CLK_NF[7:0]
Definition
No Decimation
Input Every Second Sample
Input Every Fourth Sample
D3
D3
D3
D2
D2
D2
CLK_RATIO[2:0]
D1
D1
D1
for details.
5.5.1,
D0
D0
D0
[3:0]
[7:3]
[2:0]