L64704 LSI Logic Corporation, L64704 Datasheet - Page 128

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

5.7.3
Power Level
5.8
Output Control
5-24
V
The L64704 stores the AGC loop control voltage in the PWR_LVL[7:0]
register (Group 3, APR 8), where the microcontroller can monitor it. The
relation between the loop voltage V
The PWRP pin uses an open drain buffer that allows you to apply an
external V
Because the output of the matched filter is quantized to three bits for the
subsequent Viterbi decoder, the L64704’s Output Control properly
adjusts the level of the output signals.
The microcontroller can adjust the level of the demodulated DEMI and
DEMQ output signals using the SCALE register (Group 4, APR 21). The
SCALE register multiplies the results of the matched filter before it is
truncated to the 3-bit outputs.
When the PWR_REF register (Group 4, APR 19) is set to its recom-
mended value of 84, SCALE[7:0] should be set to 158. In this case, the
spacing for the 3-bit quantized outputs DEMI and DEMQ is equal to a/8,
where a is the eye amplitude of the noise free matched filter output.
Refer to
SCALE[7:0]should be set according to the following table:
Viterbi Rate
1/2
Demodulator Module Functional Description
AGC
2/3
5/6
=
Figure
PWR_LVL
--------------------------- -
REF
3/4
7/8
256
voltage of 5 V even if the L64704 is powered at 3.3 V.
5.13.
Scale
158
190
V
REF
AGC
and the PWR_LVL register is: