L64704 LSI Logic Corporation, L64704 Datasheet - Page 193

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Equation B.1
Figure B.2
AGC Loop Control
B.2.2
Clock Loop
SCALE[7:0]; Group 4, APR 21 – This parameter controls the internal
signals DEMI and DEMQ (see
the loop itself, but it is related to PWR_REF by
So if PWR_REF = 84, then SCALE = 158.
PWRP Pin – Connect the L64704’s PWRP output pin to 5 volts using a
470 ohm pull-up resistor. The PWRP pin is then connected to an RC loop
filter with a time constant of ~ 60 microseconds.
to connect the PWRP pin to the AGC circuit.
PWR
For more information on the AGC loop, see
Control (AGC).”
The design of the board should keep the two
CLK_VCON and CLK_VCOP parallel and minimize the distance from the
L64704 output to the op-amp’s input.
The microcontroller software has limited control over the clock loop. Set
the loop’s bandwidth according to
shows the registers that are used to control the clock loop and
5.5, “Channel Clock Recovery”
L64704 QPSK Demodulator Debugging Tips
SCALE
2 PWR_REF
N
P
5 V
R ~ 470 ohm
=
Figure 1.1
2047
explains their function.
R
Table 5.2
AGC
~ 30K
on
Section 5.7, “Automatic Gain
page
on
page
Equation
C
Figure B.2
AGC
(Sigma Delta) lines
1-2). It does not affect
~ 2.2 nF
5-8.
V
AGC
B.1.
Table B.3
shows how
Section
B-5