L64704 LSI Logic Corporation, L64704 Datasheet - Page 182
![no-image](/images/no-image-200.jpg)
L64704
Manufacturer Part Number
L64704
Description
Satellite Decoder Technical Manual 5/97
Manufacturer
LSI Logic Corporation
Datasheet
1.L64704.pdf
(220 pages)
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Figure A.1
Quick Overview of the
Serial Bus
A-2
Serial Bus Compliant Device
Serial Host Interface mode is selected by driving the HOST_MODE input
pin to LOW. In Serial Host Interface mode, data is transferred on the
SDATA pin, synchronized to a serial clock that is input on the LSB of the
Host Data Bus, D0. The serial data clock can have a maximum frequency
of 400 kHz. The remaining Host Data Bus pins, D[7:1], are used to input
the slave address that is required by the serial bus protocol.
The bus master always generates the clock and cycle start and stop con-
ditions.
using the Serial Bus Protocol.
Programming the L64704 Using the Serial Bus Protocol
Figure A.2
Overview of the Serial Bus
gives an overview of the Read and the Write cycles
Serial Bus Compliant Device
5.0 V
SDATA
D[0]
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