L64704 LSI Logic Corporation, L64704 Datasheet - Page 54

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.5.3
Group 3,
APR 4, 5
Viterbi Bit Error
Count
3.5.4
Group 3,
APR 6
Control Input
and SNR
3-22
When read, this register presents a count of the number of Viterbi
decoder bit errors found during the time period specified by VMDC2
(Group 4, APR [5:5]). VBERC is 16-bits long, where the LSB is found on
APR 4, bit 0, and the MSB on APR 5, bit 7. The actual number of errors
is equal to four times VBERC. VBERC is updated each time that a Viterbi
error is encountered, and it is reset at the beginning of each VMDC2
period.
Read/Write: R
This register contains the Control Input bit(s), the Demodulator SNR bit,
and the five upper bits of the Measured VCO Frequency. The Control
Input bit(s) and the Demodulator SNR bit are discussed here, the
Measured VCO Frequency field CAR_VCOF[13:8], is discussed in the
next section.
Read/Write: R/W
Demod_SNR Demodulator Signal to Noise Ratio
XCTR_IN
L64704 Registers
APR
APR
APR
4
5
6
Demod
_SNR
D7
D7
D7
XCTR_IN
When read, this bit gives an indication of the SNR. When
the SNR is bad, this bit is 0; when it is good, this bit is 1.
A “bad” SNR is above the threshold; a “good” SNR is
below the threshold. See
Estimator,”
External Control Input Bit
When read, this bit shows the logic level applied to the
External Control Input (XCTR_IN) pin.
D6
D6
D6
Viterbi Bit Error Rate Count High Byte, VBERC[15:8]
Viterbi Bit Error Rate Count Low Byte, VBERC[7:0]
D5
D5
D5
and
Figure 5.7
D4
D4
D4
CAR_VCOF[13:8]
Section 5.6.2.1, “Phase Error
D3
D3
D3
for details.
D2
D2
D2
Reset Value: 0x0000
Reset Value: 0x0000
D1
D1
D1
D0
D0
D0
7
6