L64704 LSI Logic Corporation, L64704 Datasheet - Page 35

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Table 3.2 (Cont.)
Register Map
Group APR
3
4
(Sheet 2 of 4)
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
Bit(s)
7
6
5:0
7:0
7:0
5
4
3
2
1
0
5:0
5:0
5:0
5:0
7
5
4:0
7:5
4
3
1:0
7:0
7:0
7:0
7:0
7:0
7:0
7
1:0
L64704 Register Overview
R/W Description
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W Phase-Locked Loop Config. Param. N
R/W Phase-Locked Loop Config. Param. S
R/W (I, -Q) Symbol Format
R/W QPSK/BPSK Format Select
R/W Phase-Locked Loop Config. Param. T
R/W Viterbi Code Rate
R/W Transport Error Indicator Select
R/W Select SYNC 2 Modified Algorithm
R/W VCO Frequency Range for PLL Module
R/W Viterbi Maximum Data Bit Count 1
R/W Viterbi Maximum Data Bit Count 2, Low
R/W Viterbi Maximum Data Bit Count 2, Middle VMDC2[15:8]
R/W Viterbi Maximum Data Bit Count 2, High
R/W Viterbi Maximum Bit Error Count
R/W Synchronization Word
R/W Bit Error Rate Monitor
R/W Mismatching Bits, Tracking Mode, Sync2
Demodulator Signal to Noise Ratio
External Control Bit Input
Measured VCO Frequency, Upper Bits
Measured VCO Frequency, Lower Byte
AGC Loop Voltage Meter
Carrier Frequency Lock Flag
Carrier Phase Lock Flag
Clock Frequency Lock Flag
Stage 3 Synchronization Flag
Stage 2 Synchronization Flag
Stage 1 Synchronization Flag
RI Input Readback
RQ Input Readback
Acronym
Demod_SNR
XCTR_IN
CAR_VCOF[13:8]
CAR_VCOF[7:0]
PWR_LVL[7:0]
CAR_LCF
CAR_LC
CLK_LCF
S3
S2
S1
RI
RQ
PLL_N[5:0]
PLL_S[5:0]
IMQ
QB
PLL_T[4:0]
VCR[2:0]
TEI
SYNC2_MOD
PLL_M[1:0]
VMDC1[7:0]
VMDC2[7:0]
VMDC2[23:16]
VMBEC[7:0]
Sync[7:0]
BER
L[1:0]
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