CD2401 Intel, CD2401 Datasheet - Page 99

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.2.3.1
Datasheet
Register Name: COR2
Register Description: Channel Option 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
0
COR2 — X.21 Mode
Bits 7:6
Bit 5
Bit 4:0
FIFO Data Sequence to Implement ETC
In X.21 mode this feature is provided to simplify the transmission of both repetitive data and data
synchronized to the ‘C’ lead. The command is a sequence of four consecutive bytes supplied as
normal transmit data by the host processor (refer to
placed in the datastream to implement this are:
Byte1
Byte 2
Byte 3
Byte 4
Bit 6
0
Reserved – must be ‘0’.
Embedded Transmitter Command enable
1 = embedded command in the FIFO is detected and acted upon.
Reserved – must be ‘0’.
This must be equal to 80 hex to start a command sequence.
This byte indicates the required state of the ‘C’ lead to be synchronized with the
transmit data.
00 = set the ‘C’ lead to off
01 = set the ‘C’ lead to on
02–FF = reserved, do not use
This is the required data character for transmission. It is sent as an 8-bit character
without parity (any required parity should be included in the character by the host).
This is the count of the number of times the character should be sent. If set to ‘0’, the
character is sent continuously until more data is provided to the transmitter (but
always a minimum of three times).
Bit 5
ETC
Bit 4
0
Multi-Protocol Communications Controller — CD2401
Bit 3
0
Section 6.4 on page
Bit 2
0
83). The sequence of bytes
Motorola Hex Address: x’17
Bit 1
Intel Hex Address: x’14
0
Bit 0
0
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