CD2401 Intel, CD2401 Datasheet - Page 147

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CD2401

Manufacturer Part Number
CD2401
Description
Multi-protocol Communications Controller
Manufacturer
Intel
Datasheet
8.6.4.9
8.6.4.10
Datasheet
Register Name: RCBADRL
Register Description: Current Receive Buffer Address – lower word
Default Value: x’0000
Access: Word Read only
Register Name: RCBADRU
Register Description: Current Receive Buffer Address – upper word
Default Value: x’0000
Access: Word Read only
Bit 15
Bit 15
Bit 7
Bit 7
Bit 6
Bit 5
Bits 4:1
Bit 0
Receive Current Buffer Address – Lower (RCBADRL) Register
Receive Current Buffer Address – Upper (RCBADRU) Register
These registers contain the address of the current DMA buffer being used for receive data. These
registers are updated at the end of receive data transfers. These registers are only for the use of the
CD2401 to manage DMA transfers. In Asynchronous mode, the host can read these registers
Bit 14
Bit 14
Bit 6
Bit 6
End of Frame (set by the CD2401 and cleared by the host CPU)
0 = this buffer does not terminate a frame.
1 = this buffer terminates a frame.
End of Buffer (set by the CD2401 and cleared by the host CPU)
0 = buffer not complete.
1 = buffer complete.
When the EOB bit is set by the CD2401, the buffer is free for the host to process
(RBCNT information is updated to the number of bytes available in the buffer, and
a new buffer can be allocated).
Reserved – must be ‘0’; reads as ‘0’.
Ownership of the Transfer buffer (set by the host CPU and cleared by the CD2401)
0 = buffer not free for use by the CD2401.
1 = buffer free for use by the CD2401.
Bit 13
Bit 13
Bit 5
Bit 5
Binary Address Value, 32-bit Address bits 31:24
Binary Address Value, 32-bit Address bits 23:16
Binary Address Value, 32-bit Address bits 15:8
Binary Address Value, 32-bit Address bits 7:0
Bit 12
Bit 12
Bit 4
Bit 4
Multi-Protocol Communications Controller — CD2401
Bit 11
Bit 11
Bit 3
Bit 3
Bit 10
Bit 10
Bit 2
Bit 2
Motorola Hex Address: x’3E
Motorola Hex Address: x’3C
Bit 9
Bit 1
Bit 9
Bit 1
Intel Hex Address: x’3C
Intel Hex Address: x’3E
Bit 8
Bit 0
Bit 8
Bit 0
147

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