CD2401 Intel, CD2401 Datasheet - Page 136

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.5.3.3
136
Register Name: TISR
Register Description: Transmit Interrupt Status
Default Value: x’00
Access: Byte Read only
Bit 7
Berr
Bit 6
Bit 5
Bit 4
Bits 3:2
Bits 1:0
Transmit Interrupt Status Register (TISR)
When the host receives a transmit interrupt, the following status are provided in this register.
Bit 7
Bit 6
Bit 5
Bit 6
EOF
Transmit Active
This bit is set automatically when Ten is set, and the Fair Share logic allows the
assertion of a transmit interrupt request. It is cleared when the host CPU writes to
TEOIR.
Transmit End of Interrupt
This bit is set automatically when the host CPU writes to TEOIR while in a transmit
interrupt routine.
Unused – always returns ‘0’ when read.
Transmit Vector [1:0]
These bits are set by the CD2401 to provide the least-significant two bits of the vec-
tor supplied to the host CPU during an interrupt acknowledge cycle.
Transmit vector is decoded as: Tvct [1] = 1, and Tvct [0] = 0.
Transmit Channel Number [1:0]
These bits are set by the CD2401 to indicate the channel requiring transmit interrupt
service.
Bus Error (written by the CD2401)
0 = no bus error.
1 = bus error detected on the last transfer.
Transmit End of Frame indication (DMA mode)
This interrupt occurs when the final data character of a transmit frame is transferred
to the transmit FIFO.
Transmit End of Buffer indication (DMA mode)
EOB
Bit 5
Ten
0
1
1
0
0
Tact
0
0
1
1
0
Bit 4
UE
Teoi
0
0
0
0
1
Idle
Transmit interrupt requested, but not asserted.
Transmit interrupt is asserted.
Transmit interrupt is acknowledged.
Transmit interrupt service routine is complete.
BA/BB
Bit 3
Bit 2
Sequence of Events
0
Motorola Hex Address: x’8A
TxEmpty
Bit 1
Intel Hex Address: x’89
Datasheet
TxDat
Bit 0