CD2401 Intel, CD2401 Datasheet - Page 127

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.5.2
8.5.2.1
Datasheet
Register Name: RPILR
Register Description: Receive Priority Interrupt Match
Default Value: x’00
Access: Byte Read/Write
Bit 7
Note: Bit 7 of this register always reads back as ‘0’. When each of the three PILRs is programmed with
MLvl[1:0]
TLvl[1:0]
Receive Interrupt Registers
Receive Priority Interrupt Level Register (RPILR)
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2401 interrupt types (that is, modem,
transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2401 compares
bits 0–6 in this register with A[6:0] to determine if the acknowledge level is correct. The value
programmed in the MSB of the register has no effect on the IACK cycle.
RPILR must contain the code used to acknowledge receive interrupts.
the same value, automatic internal prioritization is activated, with receive as the highest priority,
followed by transmit and modem.
Bit 6
These bits hold a previously-active interrupt now nested.
These bits hold the oldest interrupt now nested two bits deep.
Bit 5
CLvl [1]
0
0
1
1
User-Assigned Priority Match Value
Bit 4
CLvl [0]
Multi-Protocol Communications Controller — CD2401
0
1
0
1
No interrupt active; CAR provides the current channel
number
Currently in a modem interrupt service, MIR provides the
current channel number.
Currently in a transmit interrupt service, TIR provides the
current channel number.
Currently in a receive interrupt service, RIR provides the
current channel number.
Bit 3
Bit 2
Function
Motorola Hex Address: x’E1
Bit 1
Intel Hex Address: x’E3
Bit 0
127