CD2401 Intel, CD2401 Datasheet - Page 131

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

Datasheet
Register Name: RISRl
Register Description: Receive Interrupt Status - low
Default Value: x’00
Access: Byte Read only
Register Name: RISRl
Register Description: Receive Interrupt Status Register - low
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 7
LVal
0
Bisynchronous Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2:0
RISRl - X.21 Mode
For X.21 operation, the CTS* pin is used as the ‘I’ lead for DTE or ‘C’ lead for DCE; a low level
on CTS* is interpreted as an ON condition and a high level as an OFF condition.
Bit 7
SCdet2
EOF
Bit 6
Bit 6
Reserved – reads as ‘0’.
End of Frame
This bit indicates that a valid end of frame was received, and the frame is essentially
complete.
Receive Abort
This bit indicates that an abort sequence terminating the frame was received.
Receive CRC error
This bit indicates that a frame with a valid end of frame was received, but the FCS
was not correct.
Overrun Error
This bit indicates that the receiver buffer and FIFO were overrun. At least one new
character was received, but lost since there was no room available in the receiver
buffer and/or FIFO. The OE status is set on the last character received before the
overrun occurred.
Reserved – reads as ‘0’.
Lead Value
0 = OFF
1 = ON
SCdet1
RxAbt
Bit 5
Bit 5
SCdet0
CRC
Bit 4
Bit 4
Multi-Protocol Communications Controller — CD2401
Bit 3
Bit 3
OE
OE
Bit 2
Bit 2
PE
0
Motorola Hex Address: x’89
Motorola Hex Address: x’89
Bit 1
Bit 1
Intel Hex Address: x’8A
Intel Hex Address: x’8A
0
0
LChg
Bit 0
Bit 0
0
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