CD2401 Intel, CD2401 Datasheet - Page 98

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
98
Register Name: COR2
Register Description: Channel Option 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
LRC
Note: In ASCII mode, data is 7 bits with LRC (odd parity) checking only. In EBCDIC mode, data is 8 bits
Bit 0
COR2 — Bisync Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:0
with CRC checking only.
BCC
Bit 6
1 = CTS* is evaluated prior to the transmission of each character. If CTS* is asserted
low, that character is transmitted completely. If CTS* is high, that character trans-
mission is held until CTS* goes low.
DSR* Automatic Enable
0 = the receiver input enable is independent of the DSR* input pin.
1 = DSR* is evaluated at the end of each received character. If DSR* is asserted low,
the receiver input is enabled for the next character. If DSR* is high, the receiver is
disabled until DSR* goes low.
Longitudinal Redundancy Check
0 = CRC16 used for BCC.
1 = LRC used for BCC.
BCC append
0 = receive BCC is not passed to the host at end of frame.
1 = receive BCC is passed to the host at end of frame.
EBCDIC
0 = ASCII character set in use.
1 = EBCDIC character set in use.
CRC Transmit Inverted
0 = CRC is transmitted inverted (CRC V.41).
1 = CRC is not transmitted inverted (CRC-16).
Extra SYN characters [3:0]
This field determines the number of extra SYN characters that are transmitted before
a frame starts. The two required SYNs are not included in this count. This is a binary
encode field in which the two required SYNs are followed by the encoded number
of characters (0000 = no extra characters; 1111 = 15 extra characters).
EBCDIC
Bit 5
CRCNinv
Bit 4
SYN3
Bit 3
SYN2
Bit 2
Motorola Hex Address: x’17
SYN1
Bit 1
Intel Hex Address: x’14
Datasheet
SYN0
Bit 0