CD2401 Intel, CD2401 Datasheet - Page 105

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.2.6
Datasheet
Register Name: COR5
Register Description: Channel Option 5
Default Value: x’00
Access: Byte Read/Write
DSRod
Bit 7
Channel Option Register 5 (COR5)
This register defines the current state change options to be monitored.
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:0
CDod
Bit 6
In Asynchronous mode, a Good Data transfer is initiated for the number of charac-
ters in the FIFO greater than the specified threshold. Receive timeout and the occur-
rence of a receive data exception are also cause to initiate a receive transfer.
In Synchronous mode, data transfer is initiated when the number of characters in the
FIFO is greater than the specified threshold. An EPF is also cause to initiate a receive
transfer.
For transmit operation, the CD2401 attempts to refill the transmit FIFO when the
empty space in the FIFO is greater than the set threshold. In the case of synchronous
frame transmissions, the CD2401 stops refilling the transmit FIFO once the last
character in the frame transfers to the FIFO.
Detect zero-to-one transition on DSR*
1 = detect zero-to-one transition on DSR* input (one-to-zero transition on
MSVR[7])
Detect zero-to-one transition on CD*
1 = detect zero-to-one transition on CD* input (one-to-zero transition on MSVR[6])
Detect zero-to-one transition on CTS*
1 = detect zero-to-one transition on CTS* input (one-to-zero transition on MSVR[5])
Reserved – must be ‘0’.
Receive Flow Control FIFO Threshold
These 4 bits (binary-encoded field) define the receive FIFO hardware flow control
threshold. It sets the threshold in the receive FIFO where the automatic hardware
(DTR/DSR) flow control is activated. A threshold value of ‘0’ disables the hardware
flow control mechanism. When the number of characters in the receive FIFO
exceeds this threshold, the DTR* pin deasserts. When the number of characters is
equal to or less than the threshold, DTR* is asserted.
CTSod
Bit 5
Bit 4
0
Multi-Protocol Communications Controller — CD2401
Bit 3
Rx Flow Control Threshold
Bit 2
Motorola Hex Address: x’14
Bit 1
Intel Hex Address: x’17
Bit 0
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