CD2401 Intel, CD2401 Datasheet - Page 154
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
CD2401
Manufacturer Part Number
CD2401
Description
Multi-protocol Communications Controller
Manufacturer
Intel
Datasheet
1.CD2401.pdf
(176 pages)
- Current page: 154 of 176
- Download datasheet (918Kb)
CD2401 — Multi-Protocol Communications Controller
8.7.2.2
8.7.3
8.7.3.1
154
Register Name: RTPRh
Register Description: Receive Timeout Period – high byte
Default Value: x’00
Access: Byte Read/Write – Async mode only
Register Name: GT1
Register Description: General Timer 1
Default Value: x’00
Access: Word Read/Write
Register Name: GT1l
Register Description: General Timer 1 – low byte
Default Value: x’00
Access: Byte Read/Write
Bit 15
RxEn
Bit 7
Bit 7
Bit 7
Receive Timeout Period Register – High (RTPRh) – Async Mode only
The value in this register sets the receive data timeout period in Async mode; this register is used as
general-purpose timers in Sync modes (see
receive FIFO or the last data is transferred from the FIFO to the host, the receive timer (an internal
timer) is reloaded with the RTPR. The receive timer decrements on each ‘tick’ of the prescaler
counter, this period is controlled in TPR. If the receive timer reaches zero, it causes a receive data
interrupt.
The register can be accessed as a single 16-bit word, or as two byte values.
General Timer 1 (GT1) Register
General Timer 1 – Low (GT1l) – Sync Modes only
Bit 14
Bit 6
Bit 6
RxFloff
Bit 6
Bit 13
Bit 5
Bit 5
RxFlon
Bit 5
Bit 12
Binary Value bits 15:8
Bit 4
Bit 4
Binary Value bits 7:0
Binary Value
Bit 4
0
Section
–
Bit 11
Bit 3
Bit 3
Sync Modes only
8.7.3). As each character is moved into the
TxEn
Bit 3
Bit 10
Bit 2
Bit 2
TxFloff
Bit 2
Motorola Hex Address: x’2B
Motorola Hex Address: x’2A
Bit 1
Bit 9
Bit 1
Intel Hex Address: x’28
Intel Hex Address: x’28
TxFlon
Motorola Hex Address: x’24
Bit 1
Datasheet
Intel Hex Address: x’27
Bit 0
Bit 8
Bit 0
Bit 0
0
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