CD2401 Intel, CD2401 Datasheet - Page 151

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.6.5.8
Datasheet
Register Name: BTBSTS
Register Description: Transmit Buffer B Status Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Berr
B Transmit Buffer Status (BTBSTS) Register
These registers contain the status of the associated transmit buffer and enables successive buffers to
be passed between the host and the CD2401.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
To start transmission of a buffer, the host must set the A/BTBADR and A/BTBCNT registers, and
then set the 2401own bit. If the CD2401 is to generate and send the CRC for the frame, the
FCSApd (COR2[6]) must be set. If the buffer contains the end of a frame, the EOF bit must also be
set. When the buffer has been sent, the EOB bit is set by the CD2401, and the 2401own bit is reset
allowing a new buffer to be allocated.
When the Append is bit data can be added to the buffer after transmission begins. In this mode, the
host sets ATADR and ATCNT as normal, but when new data is appended to the buffer, the A/
BTBCNT can be updated. When the A buffer is used in Append mode, the CD2401 does not set the
Bit 6
EOF
Bus Error (set by the CD2401 and cleared by the host CPU)
0 = no bus error.
1 = bus error occurred on the last transfer; the suspect address is available in
TCBADR.
End of Frame (set and cleared by host CPU)
0 = this buffer is not the last in frame/block.
1 = this buffer is the last in frame/block.
End of a transmit buffer reached (DMA supported transfers only)
The end of one of the host-supplied transmit buffers has been reached. This bit is set
by the CD2401 and cleared by the host CPU.
Underrun Error
When this bit is set it indicates that a transmit underrun occurred because the buffer
was not available.
Append (Asynchronous mode; set and cleared by the host CPU)
0 = no data is appended to the buffer.
1 = data can be appended to buffer after transfer starts.
Reserved – must be ‘0’; reads as ‘0’.
Interrupt
0 = no interrupt required after the buffer is sent.
1 = interrupt required after the buffer is sent.
Ownership of transfer buffer (set by the host CPU and cleared by the CD2401)
0 = buffer not ready to be used by the CD2401.
1 = buffer is ready for the CD2401 to transmit.
EOB
Bit 5
Bit 4
UE
Multi-Protocol Communications Controller — CD2401
Append
Bit 3
Bit 2
0
Motorola Hex Address: x’5E
INTR
Bit 1
Intel Hex Address: x’5D
2401own
Bit 0
151