CD2401 Intel, CD2401 Datasheet - Page 21

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

4.0
4.1
4.1.1
Datasheet
GFRCR
CAR
Name
Global Firmware Revision Code Register
Channel Access Register
Register Table
The registers in the CD2401 are either Global or Per-Channel. The column ‘Address mode’ in the
memory map in the following tables defines this attribute for each register. Only one set of Global
registers exists. The Global registers are accessible by the host at any time. Four sets of Per-
Channel registers exist; the set accessible at any one time is determined by the currently active
channel number. The channel number is selected by the host in normal (non-interrupt) processing
by writing to the Channel Access register. The channel number in the Channel Access register
remains in force until changed by the host. The channel number is provided automatically by the
CD2401 during interrupt service routines and DMA transfers.
In the following list, some register locations appear twice. They have different names and
functions for asynchronous and synchronous protocol operations. See
this datasheet for detailed descriptions of all register functions.
Memory Map
The following notes are applicable for
NOTES:
Global Registers
1. Address mode G: Global register — one set is always accessible.
2. INT
3. MOT
Address mode P: Per-Channel register — four sets, one per channel, accessible thgough CAR
or interrupt context.
Description
address for Intel-style processor.
address for Motorola-style processor.
Multi-Protocol Communications Controller — CD2401
Section 4.1.1
Mode
Addr.
G
G
1
INT
EC
82
through
2
Section
MOT
EE
81
3
4.1.7.
Chapter 8.0 on page 92
Size
B
B
Access
R/W
R/W
Page
92
92
of
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