CD2401 Intel, CD2401 Datasheet - Page 58

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
5.5
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To retry the buffer from the failure point, the CPU should set the 2401own bit (A/BRBSTS[0]); the
CPU should not set the TermBuff bit when writing to REOIR at the end of the interrupt. This
causes the last transfer to be retried; should a bus error occur again, the above procedure is
repeated. The CPU should check to ensure that a bad location is not continually retried.
Bit Rate Generation and Data Encoding
BRG and DPLL Operation
Data clocks are generated in the CD2401 by feeding one of a number of clock sources into a
programmable divider. The clock source and divisor are user-programmable separately for each
channel and direction. Clock options are programmed in TCOR and RCOR. The divisors are
programmed in TBPR and RBPR. The possible clock sources are as follows:
Transmit
Receive
The CLK input is nominally 35 MHz.
The divisor can be programmed for values from 1–255. To maximize the accuracy of edge
detection in Asynchronous and DPLL modes, the highest frequency clock and largest divisor
combination should be selected.
An external clock input can be used, and it can be at a multiple of the desired bit rate. If so, the
appropriate divisor value must be loaded into the Bit Rate Period register. If the external clock is at
the desired bit rate, (1 clock) a value of 01h must be loaded into the associated Bit Rate Period
register.
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Clk 0 – CLK input 8
Clk 1 – CLK input 32
Clk 2 – CLK input 128
Clk 3 – CLK input 512
Clk 4 – CLK input 2048
TXCIN pin
Receive bit clock
Clk 0 – CLK input 8
Clk 1 – CLK input 32
Clk 2 – CLK input 128
Clk 3 – CLK input 512
Clk 4 – CLK input 2048
RXCIN pin
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