CD2401 Intel, CD2401 Datasheet - Page 42

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
5.2.4.2
5.2.5
5.2.5.1
5.2.5.2
42
Highest priority: Receive Interrupt register
Lowest priority: Modem Interrupt register
Systems with Interrupt Controllers
Some systems use an interrupt controller that supplies its own vector during the interrupt
acknowledge cycle. To function properly, the CD2401 needs an IACK cycle in response to its
interrupt request. These systems can decode three distinct locations from the CD2401 to produce
an IACKIN* instead of CS*. The PILRs should be programmed with the addresses of these three
locations.
Alternatively, a single location can be decoded and the three PILRs given identical values as
described above. In either case, the host should read one of these locations before the first access to
the device in an interrupt service routine. The CD2401 enters its interrupt acknowledge context for
the proper type and channel, and the data returned is the device interrupt vector from the LIVR.
Multi–CD2401 Systems
Multiple CD2401s can be chained together for systems requiring more than four channels. Each
group of interrupt request lines (IREQn*) can be connected in a parallel wired-OR fashion. The
system Interrupt Acknowledge signal is connected to the IACKIN* pin of the first device, and its
IACKOUT* is then connected to the IACKIN* of the next device, and so on, forming a chain of
CD2401s.
Keep-and-Pass Logic
The acceptance of an interrupt acknowledge cycle by the CD2401 depends on whether the part is
requesting service and whether the least-significant seven address bits match the contents of the
appropriate PILR. The following rules apply to the keep and pass logic.
Fair Share Scheme
When multiple CD2401 are chained, the Fair Share logic in these devices guarantees that the
interrupts from all CD2401s in the system are presented to the host with equal urgency. There is no
positional hierarchy in the interrupt scheme, that is, the CD2401 farthest from the host has as equal
a chance of getting its interrupts through as that of the CD2401 nearest to the top of the interrupt
chain. The Fair Share scheme is transparent to the user, and no enabling or disabling is required.
1. If the CD2401 does not have an interrupt asserted, the interrupt acknowledge is passed out on
2. If the CD2401 is asserting one or more of its interrupts, but the interrupt priority levels driven
3. If the CD2401 is asserting an interrupt, and the interrupt priority level on the address bus
IACKOUT*.
on the address bus by the host do not match the contents of the appropriate PILR, this interrupt
acknowledge is also passed out on IACKOUT*.
matches the PILR for that interrupt type, the interrupt acknowledge is accepted by the CD2401
and the vector from the LIVR is driven onto the data bus.
Transmit Interrupt register
Datasheet